FIG. 1 shows a block diagram of a sigma-delta analogue/digital converter (SD-ADC). This has a closed control loop which includes a loop filter 1 (frequently also referred to as a noise-shaping filter), a quantizer 2 and a digital/analogue converter 3 (DAC). The SD-ADC illustrated in FIG. 1 is a so-called continuous-time SD-ADC, that is to say the loop filter 1 of the SD-ADC is an analogue, continuous-time filter, whose output value is valid throughout the entire time period. In contrast, so-called switched capacitor SD-ADCs are known from the prior art, whose loop filters have capacitances which are switched in order to model resistive filter components, and in which case the output signal is valid only at specific times.
The SD-ADC in FIG. 1 has an analogue signal X that is to be converted applied to its input. The difference between the analogue input signal X and the output signal from the DAC 3 is fed to the analogue loop filter 1, whose output side drives the quantizer 2. The quantizer 2 generates an oversampled digital signal Y on the output side, whose clock rate corresponds to the clock rate of the signal clk used to clock the quantizer 2. The quantizer 2 thus represents an analogue/digital converter. The mean value of the signal Y corresponds to the analogue input signal X. The SD-ADC illustrated in FIG. 1 is a multilevel SD-ADC (also referred to as a multibit SD-ADC). In the case of a multilevel SD-ADC the quantizer 2, as a multilevel or multibit quantizer, has a plurality of N quantization thresholds. In the typical implementation of the quantizer 2 as a flash quantizer, the quantizer has N comparators which operate in parallel, in which case each comparator has a specific associated reference REFj, where REFj<REFj+1. The references REFj are typically reference voltages. However, it is also feasible to use reference currents as references.
If the input signal to the quantizer 2 is in the region above REFj and below REFj+1, then all of the comparators with reference voltages of less than or equal to REFj produce a logic 1 at their output, while the comparators with reference voltages of greater than or equal to REFj+1 produce a logic 0 at their output. The resultant code of the output signal Y from the quantizer 2, which output signal Y has a length of N bits and results from the combination of the binary comparator output signals, is referred to, by analogy with a liquid thermometer, as a “thermometer code”.
The output signal Y from the quantizer 2 is converted by means of the DAC 3 to an analogue signal which is compared with the analogue input signal X. When the control loop is in the steady state, the analogue input signal X and the output signal from the DAC 3 correspond to one another.
The loop illustrated in FIG. 1 is typically followed by a code converter (not illustrated) which converts the output signal Y from the quantizer 2 from the thermometer-code representation to a binary-code representation. Furthermore, a digital low-pass filter and a decimator (not illustrated) are arranged on the output side of the code converter, with the low-pass filter carrying out an averaging process, and with the decimator reducing the sampling rate.
The performance of the multilevel SD-ADC is governed primarily by the linearity of the internal DAC 3. The DAC 3 in general has N unit elements which—if no code conversion is carried out in the quantizer 2—are activated or deactivated as a function of the thermometer-code output signal, which has a length of N bits, from the quantizer 2. The unit elements are typically switchable unit current sources, with the output signal from the DAC 3 being obtained from the superimposition of the currents from the N unit current sources. The unit elements of the DAC 3 are ideally completely identical. In a real DAC, the unit elements are, however, slightly different, that is to say the output currents from the unit current sources are not completely identical in the activated state. There is thus a so-called mismatch, which results in non-linear distortion with respect to the output signal from the DAC 3. Since the output signal from the DAC 3 is applied to the control loop in the same way as the input signal X of the SD-ADC, any non-ideal property of the output signal from the DAC 3 is not suppressed in the control loop, and is evident as distortion in the signal Y.
In order to improve the linearity of the DAC 3, it is known for a so-called DEM block (DEM—dynamic element matching; frequently also referred to as a randomizer or scrambler block) to be provided directly at the input of the DAC 3 or within the DAC 3 (see FIG. 2). This results in the same unit elements in the DAC 3 not always being activated, but in different unit elements DAC 3 being activated at different times for a specific output signal from the quantizer 2, in which case the number of active unit elements remains constant. The linearity error of the DAC 3 is in this way reduced when averaged over time. The scrambling of the association of the unit elements of the DAC 3 can be achieved by dynamic scrambling of the code of the output signal Y from the quantizer 2, that is to say by interchanging the digits in the code signal. By way of example, a code “00111000” is generated on scrambling of a thermometer code “11100000” with a length of 8 bits. The scrambling process can be carried out using various DEM algorithms. DEM algorithms which are based on noise shaping are particularly important, in which the influence of the mismatch between the DAC unit elements is initially randomly distributed, and is then removed from the signal band.
In order to carry out the code scrambling, the DEM block 4 has digital logic which has a latency time, that is to say the output signal of the DEM block 4 reacts to a change in the signal Y only after a certain delay. This latency time acts as a dead time in the control loop and causes a deterioration in the stability characteristics of the control loop.
It is known from the document U.S. Pat. No. 6,346,898 B1 that any deterioration in the stability of the control loop caused by code scrambling can be overcome by placing a DEM block upstream of the reference inputs of the comparators within the quantizer 2′ rather than a DEM block 4 being placed between the output of the quantizer 2 and the input of the DAC 3 (see FIG. 3). In an SD-ADC such as this, the association between the references and the individual comparators in the quantizer 2′ is dynamically scrambled using a predetermined DEM algorithm. This approach is thus referred to as dynamic element matching in a reference path.
As a result of the scrambling of the references, different output bit lines of the signal Y are activated at different sampling times for one specific input signal to the quantizer 2′. Since each comparator output is permanently connected to one unit element in the DAC 3, different unit elements in the DAC 3 are thus also activated at different sampling times. The effect of the DEM block located outside the control loop, as shown in FIG. 3, is thus analogous to that of the DEM block 4 arranged within the control loop, as shown in FIG. 2, although the dynamic scrambling process shown in FIG. 3 does not involve any additional dead time within the control loop. Furthermore, in the case of the approach illustrated in FIG. 3, the influence of any mismatch within the quantizer 2′ (for example in the production of the references or with respect to the comparators themselves) is randomly distributed, and is removed from the signal band.
A network which comprises a resistor chain, coming from identical resistors, and identical current sources feeding the nodes in the resistor chain is known from the document “A Monolithic Microsystem for Analog Synthesis of Trigonometric Functions and their Inverses”, G. Gilbert, IEEE Journal of Solid-state Circuits, Vol. 17, pages 1179–1191, December 1982. If the resistor chain is fed with a differential input voltage, Ex, this results in a parabolic potential profile over the individual nodes in the resistor chain. The maximum in the parabolic potential profile for the situation where Ex=0 is located at the central node in the resistor chain, and migrates in one direction or the other when the voltage Ex is increased or decreased.